// Memory Configuration File // // Description: // A memory configuration file contains commands that define the legally // accessible areas of memory for your specific board. Useful for example // when the debugger tries to display the content of a "char *" variable, // that has not yet been initialized. // In this case the debugger may try to read from a bogus address, which // could cause a bus error. // // Board: // Freescale M5235BCCKIT // // Memory Map: // -------------------------------------------------------------------- range 0x00000000 0x001FFFFF 4 Read // 2 Mbytes External Flash range 0x10000000 0x10FFFFFF 1 ReadWrite // 16 Mbyte SDRAM reserved 0x11000000 0x1FFFFFFF range 0x20000000 0x2000FFFF 1 ReadWrite // 64 Kbytes Internal SRAM reserved 0x20010000 0x3FFFFFFF reserved 0x40200000 0xfFFFFFFF // Memory Mapped Registers (IPSBAR= 0x40000000): // ------------------------------------------------------------------- // System Control Module Registers range 0x40000000 0x40000003 4 ReadWrite // IPSBAR reserved 0x40000004 0x4000000F range 0x40000010 0x40000010 1 ReadWrite // CRSR range 0x40000011 0x40000011 1 ReadWrite // CWCR range 0x40000012 0x40000012 1 ReadWrite // LPICR range 0x40000013 0x40000013 1 ReadWrite // CWSR range 0x40000014 0x40000017 4 ReadWrite // DMAREQC reserved 0x40000018 0x4000001B range 0x4000001C 0x4000001F 4 ReadWrite // MPARK range 0x40000020 0x40000020 1 ReadWrite // MPR reserved 0x40000021 0x40000023 range 0x40000024 0x40000024 1 ReadWrite // PACR0 range 0x40000025 0x40000025 1 ReadWrite // PACR1 range 0x40000026 0x40000026 1 ReadWrite // PACR2 range 0x40000027 0x40000027 1 ReadWrite // PACR3 range 0x40000028 0x40000028 1 ReadWrite // PACR4 reserved 0x40000029 0x40000029 range 0x4000002A 0x4000002A 1 ReadWrite // PACR5 range 0x4000002B 0x4000002B 1 ReadWrite // PACR6 range 0x4000002C 0x4000002C 1 ReadWrite // PACR7 reserved 0x4000002D 0x4000002D range 0x4000002E 0x4000002E 1 ReadWrite // PACR8 reserved 0x4000002F 0x4000002F range 0x40000030 0x40000030 1 ReadWrite // GPACR0 reserved 0x40000031 0x40000031 range 0x40000032 0x40000032 1 ReadWrite // GPACR1 reserved 0x40000033 0x4000003F // SDRAM Registers range 0x40000040 0x40000041 2 ReadWrite // DCR reserved 0x40000042 0x40000047 range 0x40000048 0x4000004B 4 ReadWrite // DACR0 range 0x4000004C 0x4000004F 4 ReadWrite // DMR0 range 0x40000050 0x40000053 4 ReadWrite // DACR1 range 0x40000054 0x40000057 4 ReadWrite // DMR1 reserved 0x40000058 0x4000007F // Chip Select Module Registers range 0x40000080 0x40000081 2 ReadWrite // CSAR0 reserved 0x40000082 0x40000083 range 0x40000084 0x40000087 4 ReadWrite // CSMR0 reserved 0x40000088 0x40000089 range 0x4000008A 0x4000008B 2 ReadWrite // CSCR0 range 0x4000008C 0x4000008D 2 ReadWrite // CSAR1 reserved 0x4000008E 0x4000008F range 0x40000090 0x40000093 4 ReadWrite // CSMR1 reserved 0x40000094 0x40000095 range 0x40000096 0x40000097 2 ReadWrite // CSCR1 range 0x40000098 0x40000099 2 ReadWrite // CSAR2 reserved 0x4000009A 0x4000009B range 0x4000009C 0x4000009F 4 ReadWrite // CSMR2 reserved 0x400000A0 0x400000A1 range 0x400000A2 0x400000A3 2 ReadWrite // CSCR2 range 0x400000A4 0x400000A5 2 ReadWrite // CSAR3 reserved 0x400000A6 0x400000A7 range 0x400000A8 0x400000AB 4 ReadWrite // CSMR3 reserved 0x400000AC 0x400000AD range 0x400000AE 0x400000AF 2 ReadWrite // CSCR3 range 0x400000B0 0x400000B1 2 ReadWrite // CSAR4 reserved 0x400000B2 0x400000B3 range 0x400000B4 0x400000B7 4 ReadWrite // CSMR4 reserved 0x400000B8 0x400000B9 range 0x400000BA 0x400000BB 2 ReadWrite // CSCR4 range 0x400000BC 0x400000BD 2 ReadWrite // CSAR5 reserved 0x400000BE 0x400000BF range 0x400000C0 0x400000C3 4 ReadWrite // CSMR5 reserved 0x400000C4 0x400000C5 range 0x400000C6 0x400000C7 2 ReadWrite // CSCR5 range 0x400000C8 0x400000C9 2 ReadWrite // CSAR6 reserved 0x400000CA 0x400000CB range 0x400000CC 0x400000CF 4 ReadWrite // CSMR6 reserved 0x400000D0 0x400000D1 range 0x400000D2 0x400000D3 2 ReadWrite // CSCR6 range 0x400000D4 0x400000D5 2 ReadWrite // CSAR7 reserved 0x400000D6 0x400000D7 range 0x400000D8 0x400000DB 4 ReadWrite // CSMR7 reserved 0x400000DC 0x400000DD range 0x400000DE 0x400000DF 2 ReadWrite // CSCR7 reserved 0x400000E0 0x400000FF // DMA Channel 0 Registers range 0x40000100 0x40000103 4 ReadWrite // SAR0 range 0x40000104 0x40000107 4 ReadWrite // DAR0 range 0x40000108 0x40000108 1 ReadWrite // DSR0 range 0x40000109 0x4000010B 1 ReadWrite // BCR0 range 0x4000010C 0x4000010F 4 ReadWrite // DCR0 // DMA Channel 1 Registers range 0x40000110 0x40000113 4 ReadWrite // SAR1 range 0x40000114 0x40000117 4 ReadWrite // DAR1 range 0x40000118 0x40000118 1 ReadWrite // DSR1 range 0x40000119 0x4000011B 1 ReadWrite // BCR1 range 0x4000011C 0x4000011F 4 ReadWrite // DCR1 // DMA Channel 2 Registers range 0x40000120 0x40000123 4 ReadWrite // SAR2 range 0x40000124 0x40000127 4 ReadWrite // DAR2 range 0x40000128 0x40000128 1 ReadWrite // DSR2 range 0x40000129 0x4000012B 1 ReadWrite // BCR2 range 0x4000012C 0x4000012F 4 ReadWrite // DCR2 // DMA Channel 3 Registers range 0x40000130 0x40000133 4 ReadWrite // SAR3 range 0x40000134 0x40000137 4 ReadWrite // DAR3 range 0x40000138 0x40000138 1 ReadWrite // DSR3 range 0x40000139 0x4000013B 1 ReadWrite // BCR3 range 0x4000013C 0x4000013F 4 ReadWrite // DCR3 reserved 0x40000140 0x400001FF // UART0 Registers range 0x40000200 0x40000200 1 ReadWrite // UMR10 (ReadWrite) / UMR20 (ReadWrite) reserved 0x40000201 0x40000203 range 0x40000204 0x40000204 1 ReadWrite // USR0 (Read) / UCSR0 (Write) reserved 0x40000205 0x40000207 range 0x40000208 0x40000208 1 Write // UCR0 reserved 0x40000209 0x4000020B range 0x4000020C 0x4000020C 1 ReadWrite // URB0 (Read) / UTB0 (Write) reserved 0x4000020D 0x4000020F range 0x40000210 0x40000210 1 ReadWrite // UIPCR0 (Read) / UACR0 (Write) reserved 0x40000211 0x40000213 range 0x40000214 0x40000214 1 ReadWrite // UISR0 (Read) / UIMR0 (Write) reserved 0x40000215 0x40000217 range 0x40000218 0x40000218 1 Write // UBG10 reserved 0x40000219 0x4000021B range 0x4000021C 0x4000021C 1 Write // UBG20 reserved 0x4000021D 0x40000233 range 0x40000234 0x40000234 1 Read // UIP0 reserved 0x40000235 0x40000237 range 0x40000238 0x40000238 1 Write // UOP10 reserved 0x40000239 0x4000023B range 0x4000023C 0x4000023C 1 Write // UOP00 reserved 0x4000023D 0x4000023F // UART1 Registers range 0x40000240 0x40000240 1 ReadWrite // UMR11 (ReadWrite) / UMR21 (ReadWrite) reserved 0x40000241 0x40000243 range 0x40000244 0x40000244 1 ReadWrite // USR1 (Read) / UCSR1 (Write) reserved 0x40000245 0x40000247 range 0x40000248 0x40000248 1 Write // UCR1 reserved 0x40000249 0x4000024B range 0x4000024C 0x4000024C 1 ReadWrite // URB1 (Read) / UTB1 (Write) reserved 0x4000024D 0x4000024F range 0x40000250 0x40000250 1 ReadWrite // UIPCR1 (Read) / UACR1 (Write) reserved 0x40000251 0x40000253 range 0x40000254 0x40000254 1 ReadWrite // UISR1 (Read) / UIMR1 (Write) reserved 0x40000255 0x40000257 range 0x40000258 0x40000258 1 Write // UBG11 reserved 0x40000259 0x4000025B range 0x4000025C 0x4000025C 1 Write // UBG21 reserved 0x4000025D 0x40000273 range 0x40000274 0x40000274 1 Read // UIP1 reserved 0x40000275 0x40000277 range 0x40000278 0x40000278 1 Write // UOP11 reserved 0x40000279 0x4000027B range 0x4000027C 0x4000027C 1 Write // UOP01 reserved 0x4000027D 0x4000027F // UART2 Registers range 0x40000280 0x40000280 1 ReadWrite // UMR12 (ReadWrite) / UMR22 (ReadWrite) reserved 0x40000281 0x40000283 range 0x40000284 0x40000284 1 ReadWrite // USR2 (Read) / UCSR2 (Write) reserved 0x40000285 0x40000287 range 0x40000288 0x40000288 1 Write // UCR2 reserved 0x40000289 0x4000028B range 0x4000028C 0x4000028C 1 ReadWrite // URB2 (Read) / UTB2 (Write) reserved 0x4000028D 0x4000028F range 0x40000290 0x40000290 1 ReadWrite // UIPCR2 (Read) / UACR2 (Write) reserved 0x40000291 0x40000293 range 0x40000294 0x40000294 1 ReadWrite // UISR2 (Read) / UIMR2 (Write) reserved 0x40000295 0x40000297 range 0x40000298 0x40000298 1 Write // UBG12 reserved 0x40000299 0x4000029B range 0x4000029C 0x4000029C 1 Write // UBG22 reserved 0x4000029D 0x400002B3 range 0x400002B4 0x400002B4 1 Read // UIP2 reserved 0x400002B5 0x400002B7 range 0x400002B8 0x400002B8 1 Write // UOP12 reserved 0x400002B9 0x400002BB range 0x400002BC 0x400002BC 1 Write // UOP02 reserved 0x400002BD 0x400002FF // I2C Registers range 0x40000300 0x40000300 1 ReadWrite // I2ADR reserved 0x40000301 0x40000303 range 0x40000304 0x40000304 1 ReadWrite // I2FDR reserved 0x40000305 0x40000307 range 0x40000308 0x40000308 1 ReadWrite // I2CR reserved 0x40000309 0x4000030B range 0x4000030C 0x4000030C 1 ReadWrite // I2SR reserved 0x4000030D 0x4000030F range 0x40000310 0x40000310 1 ReadWrite // I2DR reserved 0x40000311 0x4000033F // Queued Serial Peripheral Interface Module Registers range 0x40000340 0x40000341 2 ReadWrite // QMR reserved 0x40000342 0x40000343 range 0x40000344 0x40000345 2 ReadWrite // QDLYR reserved 0x40000346 0x40000347 range 0x40000348 0x40000349 2 ReadWrite // QWR reserved 0x4000034A 0x4000034B range 0x4000034C 0x4000034D 2 ReadWrite // QIR reserved 0x4000034E 0x4000034F range 0x40000350 0x40000351 2 ReadWrite // QAR reserved 0x40000352 0x40000353 range 0x40000354 0x40000355 2 ReadWrite // QDR reserved 0x40000356 0x400003FF // DMA Timer 0 Registers range 0x40000400 0x40000401 2 ReadWrite // DTMR0 range 0x40000402 0x40000402 1 ReadWrite // DTXMR0 range 0x40000403 0x40000403 1 ReadWrite // DTER0 range 0x40000404 0x40000407 4 ReadWrite // DTRR0 range 0x40000408 0x4000040B 4 ReadWrite // DTCR0 range 0x4000040C 0x4000040F 4 ReadWrite // DTCN0 reserved 0x40000410 0x4000043F // DMA Timer 1 Registers range 0x40000440 0x40000441 2 ReadWrite // DTMR1 range 0x40000442 0x40000442 1 ReadWrite // DTXMR1 range 0x40000443 0x40000443 1 ReadWrite // DTER1 range 0x40000444 0x40000447 4 ReadWrite // DTRR1 range 0x40000448 0x4000044B 4 ReadWrite // DTCR1 range 0x4000044C 0x4000044F 4 ReadWrite // DTCN1 reserved 0x40000450 0x4000047F // DMA Timer 2 Registers range 0x40000480 0x40000481 2 ReadWrite // DTMR2 range 0x40000482 0x40000482 1 ReadWrite // DTXMR2 range 0x40000483 0x40000483 1 ReadWrite // DTER2 range 0x40000484 0x40000487 4 ReadWrite // DTRR2 range 0x40000488 0x4000048B 4 ReadWrite // DTCR2 range 0x4000048C 0x4000048F 4 ReadWrite // DTCN2 reserved 0x40000490 0x400004BF // DMA Timer 3 Registers range 0x400004C0 0x400004C1 2 ReadWrite // DTMR3 range 0x400004C2 0x400004C2 1 ReadWrite // DTXMR3 range 0x400004C3 0x400004C3 1 ReadWrite // DTER3 range 0x400004C4 0x400004C7 4 ReadWrite // DTRR3 range 0x400004C8 0x400004CB 4 ReadWrite // DTCR3 range 0x400004CC 0x400004CF 4 ReadWrite // DTCN3 reserved 0x400004D0 0x40000BFF // Interrupt Controller Registers 0 range 0x40000C00 0x40000C03 4 Read // IPRH0 range 0x40000C04 0x40000C07 4 Read // IPRL0 range 0x40000C08 0x40000C0B 4 ReadWrite // IMRH0 range 0x40000C0C 0x40000C0F 4 ReadWrite // IMRL0 range 0x40000C10 0x40000C13 4 ReadWrite // INTFRCH0 range 0x40000C14 0x40000C17 4 Read // INTFRCL0 range 0x40000C18 0x40000C18 1 Read // IRLR0 range 0x40000C19 0x40000C19 1 Read // IACKLPR0 reserved 0x40000C1A 0x40000C40 range 0x40000C41 0x40000C41 1 Read // ICR001 range 0x40000C42 0x40000C42 1 Read // ICR002 range 0x40000C43 0x40000C43 1 Read // ICR003 range 0x40000C44 0x40000C44 1 Read // ICR004 range 0x40000C45 0x40000C45 1 Read // ICR005 range 0x40000C46 0x40000C46 1 Read // ICR006 range 0x40000C47 0x40000C47 1 Read // ICR007 range 0x40000C48 0x40000C48 1 ReadWrite // ICR008 range 0x40000C49 0x40000C49 1 ReadWrite // ICR009 range 0x40000C4A 0x40000C4A 1 ReadWrite // ICR010 range 0x40000C4B 0x40000C4B 1 ReadWrite // ICR011 range 0x40000C4C 0x40000C4C 1 ReadWrite // ICR012 range 0x40000C4D 0x40000C4D 1 ReadWrite // ICR013 range 0x40000C4E 0x40000C4E 1 ReadWrite // ICR014 range 0x40000C4F 0x40000C4F 1 ReadWrite // ICR015 range 0x40000C50 0x40000C50 1 ReadWrite // ICR016 range 0x40000C51 0x40000C51 1 ReadWrite // ICR017 range 0x40000C52 0x40000C52 1 ReadWrite // ICR018 range 0x40000C53 0x40000C53 1 ReadWrite // ICR019 range 0x40000C54 0x40000C54 1 ReadWrite // ICR020 range 0x40000C55 0x40000C55 1 ReadWrite // ICR021 range 0x40000C56 0x40000C56 1 ReadWrite // ICR022 range 0x40000C57 0x40000C57 1 ReadWrite // ICR023 range 0x40000C58 0x40000C58 1 ReadWrite // ICR024 range 0x40000C59 0x40000C59 1 ReadWrite // ICR025 range 0x40000C5A 0x40000C5A 1 ReadWrite // ICR026 range 0x40000C5B 0x40000C5B 1 ReadWrite // ICR027 range 0x40000C5C 0x40000C5C 1 ReadWrite // ICR028 range 0x40000C5D 0x40000C5D 1 ReadWrite // ICR029 range 0x40000C5E 0x40000C5E 1 ReadWrite // ICR030 range 0x40000C5F 0x40000C5F 1 ReadWrite // ICR031 range 0x40000C60 0x40000C60 1 ReadWrite // ICR032 range 0x40000C61 0x40000C61 1 ReadWrite // ICR033 range 0x40000C62 0x40000C62 1 ReadWrite // ICR034 range 0x40000C63 0x40000C63 1 ReadWrite // ICR035 range 0x40000C64 0x40000C64 1 ReadWrite // ICR036 range 0x40000C65 0x40000C65 1 ReadWrite // ICR037 range 0x40000C66 0x40000C66 1 ReadWrite // ICR038 range 0x40000C67 0x40000C67 1 ReadWrite // ICR039 range 0x40000C68 0x40000C68 1 ReadWrite // ICR040 range 0x40000C69 0x40000C69 1 ReadWrite // ICR041 range 0x40000C6A 0x40000C6A 1 ReadWrite // ICR042 range 0x40000C6B 0x40000C6B 1 ReadWrite // ICR043 range 0x40000C6C 0x40000C6C 1 ReadWrite // ICR044 range 0x40000C6D 0x40000C6D 1 ReadWrite // ICR045 range 0x40000C6E 0x40000C6E 1 ReadWrite // ICR046 range 0x40000C6F 0x40000C6F 1 ReadWrite // ICR047 range 0x40000C70 0x40000C70 1 ReadWrite // ICR048 range 0x40000C71 0x40000C71 1 ReadWrite // ICR049 range 0x40000C72 0x40000C72 1 ReadWrite // ICR050 range 0x40000C73 0x40000C73 1 ReadWrite // ICR051 range 0x40000C74 0x40000C74 1 ReadWrite // ICR052 range 0x40000C75 0x40000C75 1 ReadWrite // ICR053 range 0x40000C76 0x40000C76 1 ReadWrite // ICR054 range 0x40000C77 0x40000C77 1 ReadWrite // ICR055 range 0x40000C78 0x40000C78 1 ReadWrite // ICR056 range 0x40000C79 0x40000C79 1 ReadWrite // ICR057 range 0x40000C7A 0x40000C7A 1 ReadWrite // ICR058 range 0x40000C7B 0x40000C7B 1 ReadWrite // ICR059 range 0x40000C7C 0x40000C7C 1 ReadWrite // ICR060 range 0x40000C7D 0x40000C7D 1 ReadWrite // ICR061 range 0x40000C7E 0x40000C7E 1 ReadWrite // ICR062 range 0x40000C7F 0x40000C7F 1 ReadWrite // ICR063 reserved 0x40000C80 0x40000CDF range 0x40000CE0 0x40000CE0 1 Read // SWIACK0 reserved 0x40000CE1 0x40000CE3 range 0x40000CE4 0x40000CE4 1 Read // L1IACK0 reserved 0x40000CE5 0x40000CE7 range 0x40000CE8 0x40000CE8 1 Read // L2IACK0 reserved 0x40000CE9 0x40000CEB range 0x40000CEC 0x40000CEC 1 Read // L3IACK0 reserved 0x40000CED 0x40000CEF range 0x40000CF0 0x40000CF0 1 Read // L4IACK0 reserved 0x40000CF1 0x40000CF3 range 0x40000CF4 0x40000CF4 1 Read // L5IACK0 reserved 0x40000CF5 0x40000CF7 range 0x40000CF8 0x40000CF8 1 Read // L6IACK0 reserved 0x40000CF9 0x40000CFB range 0x40000CFC 0x40000CFC 1 Read // L7IACK0 reserved 0x40000CFD 0x40000CFF // Interrupt Controller Registers 1 range 0x40000D00 0x40000D03 4 Read // IPRH1 range 0x40000D04 0x40000D07 4 Read // IPRL1 range 0x40000D08 0x40000D0B 4 ReadWrite // IMRH1 range 0x40000D0C 0x40000D0F 4 ReadWrite // IMRL1 range 0x40000D10 0x40000D13 4 ReadWrite // INTFRCH1 range 0x40000D14 0x40000D17 4 Read // INTFRCL1 range 0x40000D18 0x40000D18 1 Read // IRLR1 range 0x40000D19 0x40000D19 1 Read // IACKLPR1 reserved 0x40000D1A 0x40000D40 range 0x40000D41 0x40000D41 1 Read // ICR101 range 0x40000D42 0x40000D42 1 Read // ICR102 range 0x40000D43 0x40000D43 1 Read // ICR103 range 0x40000D44 0x40000D44 1 Read // ICR104 range 0x40000D45 0x40000D45 1 Read // ICR105 range 0x40000D46 0x40000D46 1 Read // ICR106 range 0x40000D47 0x40000D47 1 Read // ICR107 range 0x40000D48 0x40000D48 1 ReadWrite // ICR108 range 0x40000D49 0x40000D49 1 ReadWrite // ICR109 range 0x40000D4A 0x40000D4A 1 ReadWrite // ICR110 range 0x40000D4B 0x40000D4B 1 ReadWrite // ICR111 range 0x40000D4C 0x40000D4C 1 ReadWrite // ICR112 range 0x40000D4D 0x40000D4D 1 ReadWrite // ICR113 range 0x40000D4E 0x40000D4E 1 ReadWrite // ICR114 range 0x40000D4F 0x40000D4F 1 ReadWrite // ICR115 range 0x40000D50 0x40000D50 1 ReadWrite // ICR116 range 0x40000D51 0x40000D51 1 ReadWrite // ICR117 range 0x40000D52 0x40000D52 1 ReadWrite // ICR118 range 0x40000D53 0x40000D53 1 ReadWrite // ICR119 range 0x40000D54 0x40000D54 1 ReadWrite // ICR120 range 0x40000D55 0x40000D55 1 ReadWrite // ICR121 range 0x40000D56 0x40000D56 1 ReadWrite // ICR122 range 0x40000D57 0x40000D57 1 ReadWrite // ICR123 range 0x40000D58 0x40000D58 1 ReadWrite // ICR124 range 0x40000D59 0x40000D59 1 ReadWrite // ICR125 range 0x40000D5A 0x40000D5A 1 ReadWrite // ICR126 range 0x40000D5B 0x40000D5B 1 ReadWrite // ICR127 range 0x40000D5C 0x40000D5C 1 ReadWrite // ICR128 range 0x40000D5D 0x40000D5D 1 ReadWrite // ICR129 range 0x40000D5E 0x40000D5E 1 ReadWrite // ICR130 range 0x40000D5F 0x40000D5F 1 ReadWrite // ICR131 range 0x40000D60 0x40000D60 1 ReadWrite // ICR132 range 0x40000D61 0x40000D61 1 ReadWrite // ICR133 range 0x40000D62 0x40000D62 1 ReadWrite // ICR134 range 0x40000D63 0x40000D63 1 ReadWrite // ICR135 range 0x40000D64 0x40000D64 1 ReadWrite // ICR136 range 0x40000D65 0x40000D65 1 ReadWrite // ICR137 range 0x40000D66 0x40000D66 1 ReadWrite // ICR138 range 0x40000D67 0x40000D67 1 ReadWrite // ICR139 range 0x40000D68 0x40000D68 1 ReadWrite // ICR140 range 0x40000D69 0x40000D69 1 ReadWrite // ICR141 range 0x40000D6A 0x40000D6A 1 ReadWrite // ICR142 range 0x40000D6B 0x40000D6B 1 ReadWrite // ICR143 range 0x40000D6C 0x40000D6C 1 ReadWrite // ICR144 range 0x40000D6D 0x40000D6D 1 ReadWrite // ICR145 range 0x40000D6E 0x40000D6E 1 ReadWrite // ICR146 range 0x40000D6F 0x40000D6F 1 ReadWrite // ICR147 range 0x40000D70 0x40000D70 1 ReadWrite // ICR148 range 0x40000D71 0x40000D71 1 ReadWrite // ICR149 range 0x40000D72 0x40000D72 1 ReadWrite // ICR150 range 0x40000D73 0x40000D73 1 ReadWrite // ICR151 range 0x40000D74 0x40000D74 1 ReadWrite // ICR152 range 0x40000D75 0x40000D75 1 ReadWrite // ICR153 range 0x40000D76 0x40000D76 1 ReadWrite // ICR154 range 0x40000D77 0x40000D77 1 ReadWrite // ICR155 range 0x40000D78 0x40000D78 1 ReadWrite // ICR156 range 0x40000D79 0x40000D79 1 ReadWrite // ICR157 range 0x40000D7A 0x40000D7A 1 ReadWrite // ICR158 range 0x40000D7B 0x40000D7B 1 ReadWrite // ICR159 range 0x40000D7C 0x40000D7C 1 ReadWrite // ICR160 range 0x40000D7D 0x40000D7D 1 ReadWrite // ICR161 range 0x40000D7E 0x40000D7E 1 ReadWrite // ICR162 range 0x40000D7F 0x40000D7F 1 ReadWrite // ICR163 reserved 0x40000D80 0x40000DDF range 0x40000DE0 0x40000DE0 1 Read // SWIACK1 reserved 0x40000DE1 0x40000DE3 range 0x40000DE4 0x40000DE4 1 Read // L1IACK1 reserved 0x40000DE5 0x40000DE7 range 0x40000DE8 0x40000DE8 1 Read // L2IACK1 reserved 0x40000DE9 0x40000DEB range 0x40000DEC 0x40000DEC 1 Read // L3IACK1 reserved 0x40000DED 0x40000DEF range 0x40000DF0 0x40000DF0 1 Read // L4IACK1 reserved 0x40000DF1 0x40000DF3 range 0x40000DF4 0x40000DF4 1 Read // L5IACK1 reserved 0x40000DF5 0x40000DF7 range 0x40000DF8 0x40000DF8 1 Read // L6IACK1 reserved 0x40000DF9 0x40000DFB range 0x40000DFC 0x40000DFC 1 Read // L7IACK1 reserved 0x40000DFD 0x40001003 // Fast Ethernet Controllers Registers range 0x40001004 0x40001007 4 ReadWrite // EIR range 0x40001008 0x4000100B 4 ReadWrite // EIMR reserved 0x4000100C 0x4000100F range 0x40001010 0x40001013 4 ReadWrite // RDAR range 0x40001014 0x40001017 4 ReadWrite // TDAR reserved 0x40001018 0x40001023 range 0x40001024 0x40001027 4 ReadWrite // ECR reserved 0x40001028 0x4000103F range 0x40001040 0x40001043 4 ReadWrite // MDATA range 0x40001044 0x40001047 4 ReadWrite // MSCR reserved 0x40001048 0x40001063 range 0x40001064 0x40001067 4 ReadWrite // MIBC reserved 0x40001068 0x40001083 range 0x40001084 0x40001087 4 ReadWrite // RCR reserved 0x40001088 0x400010C3 range 0x400010C4 0x400010C7 4 ReadWrite // TCR reserved 0x400010C8 0x400010E3 range 0x400010E4 0x400010E7 4 ReadWrite // PALR range 0x400010E8 0x400010EB 4 ReadWrite // PAUR range 0x400010EC 0x400010EF 4 ReadWrite // OPD reserved 0x400010F0 0x40001117 range 0x40001118 0x4000111B 4 ReadWrite // IAUR range 0x4000111C 0x4000111F 4 ReadWrite // IALR range 0x40001120 0x40001123 4 ReadWrite // GAUR range 0x40001124 0x40001127 4 ReadWrite // GALR reserved 0x40001128 0x40001143 range 0x40001144 0x40001147 4 ReadWrite // TFWR reserved 0x40001148 0x4000114B range 0x4000114C 0x4000114F 4 ReadWrite // FRBR range 0x40001150 0x40001153 4 ReadWrite // FRSR reserved 0x40001154 0x4000117F range 0x40001180 0x40001183 4 ReadWrite // ERDSR range 0x40001184 0x40001187 4 ReadWrite // ETDSR range 0x40001188 0x4000118B 4 ReadWrite // EMRBR reserved 0x4000118C 0x400FFFFF // GPIO Registers range 0x40100000 0x40100000 1 ReadWrite // PODR_ADDR range 0x40100001 0x40100001 1 ReadWrite // PODR_DATAH range 0x40100002 0x40100002 1 ReadWrite // PODR_DATAL range 0x40100003 0x40100003 1 ReadWrite // PODR_BUSCTL range 0x40100004 0x40100004 1 ReadWrite // PODR_BS range 0x40100005 0x40100005 1 ReadWrite // PODR_CS range 0x40100006 0x40100006 1 ReadWrite // PODR_SDRAM range 0x40100007 0x40100007 1 ReadWrite // PODR_FECI2C range 0x40100008 0x40100008 1 ReadWrite // PODR_UARTH range 0x40100009 0x40100009 1 ReadWrite // PODR_UARTL range 0x4010000A 0x4010000A 1 ReadWrite // PODR_QSPI range 0x4010000B 0x4010000B 1 ReadWrite // PODR_TIMER range 0x4010000C 0x4010000C 1 ReadWrite // PODR_ETPU reserved 0x4010000D 0x4010000F range 0x40100010 0x40100010 1 ReadWrite // PDDR_ADDR range 0x40100011 0x40100011 1 ReadWrite // PDDR_DATAH range 0x40100012 0x40100012 1 ReadWrite // PDDR_DATAL range 0x40100013 0x40100013 1 ReadWrite // PDDR_BUSCTL range 0x40100014 0x40100014 1 ReadWrite // PDDR_BS range 0x40100015 0x40100015 1 ReadWrite // PDDR_CS range 0x40100016 0x40100016 1 ReadWrite // PDDR_SDRAM range 0x40100017 0x40100017 1 ReadWrite // PDDR_FECI2C range 0x40100018 0x40100018 1 ReadWrite // PDDR_UARTH range 0x40100019 0x40100019 1 ReadWrite // PDDR_UARTL range 0x4010001A 0x4010001A 1 ReadWrite // PDDR_QSPI range 0x4010001B 0x4010001B 1 ReadWrite // PDDR_TIMER range 0x4010001C 0x4010001C 1 ReadWrite // PDDR_ETPU reserved 0x4010001D 0x4010001F range 0x40100020 0x40100020 1 ReadWrite // PPDSDR_ADDR range 0x40100021 0x40100021 1 ReadWrite // PPDSDR_DATAH range 0x40100022 0x40100022 1 ReadWrite // PPDSDR_DATAL range 0x40100023 0x40100023 1 ReadWrite // PPDSDR_BUSCTL range 0x40100024 0x40100024 1 ReadWrite // PPDSDR_BS range 0x40100025 0x40100025 1 ReadWrite // PPDSDR_CS range 0x40100026 0x40100026 1 ReadWrite // PPDSDR_SDRAM range 0x40100027 0x40100027 1 ReadWrite // PPDSDR_FECI2C range 0x40100028 0x40100028 1 ReadWrite // PPDSDR_UARTH range 0x40100029 0x40100029 1 ReadWrite // PPDSDR_UARTL range 0x4010002A 0x4010002A 1 ReadWrite // PPDSDR_QSPI range 0x4010002B 0x4010002B 1 ReadWrite // PPDSDR_TIMER range 0x4010002C 0x4010002C 1 ReadWrite // PPDSDR_ETPU reserved 0x4010002D 0x4010002F range 0x40100030 0x40100030 1 ReadWrite // PCLRR_ADDR range 0x40100031 0x40100031 1 ReadWrite // PCLRR_DATAH range 0x40100032 0x40100032 1 ReadWrite // PCLRR_DATAL range 0x40100033 0x40100033 1 ReadWrite // PCLRR_BUSCTL range 0x40100034 0x40100034 1 ReadWrite // PCLRR_BS range 0x40100035 0x40100035 1 ReadWrite // PCLRR_CS range 0x40100036 0x40100036 1 ReadWrite // PCLRR_SDRAM range 0x40100037 0x40100037 1 ReadWrite // PCLRR_FECI2C range 0x40100038 0x40100038 1 ReadWrite // PCLRR_UARTH range 0x40100039 0x40100039 1 ReadWrite // PCLRR_UARTL range 0x4010003A 0x4010003A 1 ReadWrite // PCLRR_QSPI range 0x4010003B 0x4010003B 1 ReadWrite // PCLRR_TIMER range 0x4010003C 0x4010003C 1 ReadWrite // PCLRR_ETPU reserved 0x4010003D 0x4010003F range 0x40100040 0x40100040 1 ReadWrite // PAR_AD reserved 0x40100041 0x40100041 range 0x40100042 0x40100043 2 ReadWrite // PAR_BUSCTL range 0x40100044 0x40100044 1 ReadWrite // PAR_BS range 0x40100045 0x40100045 1 ReadWrite // PAR_CS range 0x40100046 0x40100046 1 ReadWrite // PAR_SDRAM range 0x40100047 0x40100047 1 ReadWrite // PAR_FECI2C range 0x40100048 0x40100049 2 ReadWrite // PAR_UART range 0x4010004A 0x4010004A 1 ReadWrite // PAR_QSPI reserved 0x4010004B 0x4010004B range 0x4010004C 0x4010004D 2 ReadWrite // PAR_TIMER range 0x4010004E 0x4010004E 1 ReadWrite // PAR_ETPU reserved 0x4010004F 0x4010004F range 0x40100050 0x40100050 1 ReadWrite // DSCR_EIM range 0x40100051 0x40100051 1 ReadWrite // DSCR_ETPU range 0x40100052 0x40100052 1 ReadWrite // DSCR_FECI2C range 0x40100053 0x40100053 1 ReadWrite // DSCR_UART range 0x40100054 0x40100054 1 ReadWrite // DSCR_QSPI range 0x40100055 0x40100055 1 ReadWrite // DSCR_TIMER reserved 0x40100056 0x4010FFFF // Reset controller Module Registers range 0x40110000 0x40110000 1 ReadWrite // RCR range 0x40110001 0x40110001 1 Read // RSR reserved 0x40110002 0x40110003 // Chip Configuration Module Registers range 0x40110004 0x40110005 2 ReadWrite // CCR reserved 0x40110006 0x40110006 range 0x40110007 0x40110007 1 ReadWrite // LPCR range 0x40110008 0x40110009 2 ReadWrite // RCON range 0x4011000A 0x4011000A 1 ReadWrite // CIR reserved 0x4011000B 0x4011FFFF // Clock Module Registers range 0x40120000 0x40120003 4 ReadWrite // SYNCR range 0x40120004 0x40120007 4 Read // SYNSR reserved 0x40120008 0x4012FFFF // Edge Port Registers range 0x40130000 0x40130001 2 ReadWrite // EPPAR range 0x40130002 0x40130002 1 ReadWrite // EPDDR range 0x40130003 0x40130003 1 ReadWrite // EPIER range 0x40130004 0x40130004 1 ReadWrite // EPDR range 0x40130005 0x40130005 1 Read // EPPDR range 0x40130006 0x40130006 1 ReadWrite // EPFR reserved 0x40130007 0x4013FFFF // Watchdog Timer Module Registers range 0x40140000 0x40140001 2 ReadWrite // WCR range 0x40140002 0x40140003 2 ReadWrite // WMR range 0x40140004 0x40140005 2 Read // WCNTR range 0x40140006 0x40140007 2 ReadWrite // WSR reserved 0x40140008 0x4014FFFF // Programmable Interrupt Timer 0 Modules Registers range 0x40150000 0x40150001 2 ReadWrite // PCSR0 range 0x40150002 0x40150003 2 ReadWrite // PMR0 range 0x40150004 0x40150005 2 Read // PCNTR0 reserved 0x40150006 0x4015FFFF // Programmable Interrupt Timer 1 Modules Registers range 0x40160000 0x40160001 2 ReadWrite // PCSR1 range 0x40160002 0x40160003 2 ReadWrite // PMR1 range 0x40160004 0x40160005 2 Read // PCNTR1 reserved 0x40160006 0x4016FFFF // Programmable Interrupt Timer 2 Modules Registers range 0x40170000 0x40170001 2 ReadWrite // PCSR2 range 0x40170002 0x40170003 2 ReadWrite // PMR2 range 0x40170004 0x40170005 2 Read // PCNTR2 reserved 0x40170006 0x4017FFFF // Programmable Interrupt Timer 3 Modules Registers range 0x40180000 0x40180001 2 ReadWrite // PCSR3 range 0x40180002 0x40180003 2 ReadWrite // PMR3 range 0x40180004 0x40180005 2 Read // PCNTR3 reserved 0x40180006 0x4018FFFF // Message Digest Hardware Accelerator Registers range 0x40190000 0x40190003 4 ReadWrite // MDMR range 0x40190004 0x40190007 4 ReadWrite // MDCR range 0x40190008 0x4019000B 4 Write // MDCMR range 0x4019000C 0x4019000F 4 Read // MDSR range 0x40190010 0x40190013 4 Read // MDISR range 0x40190014 0x40190017 4 ReadWrite // MDIMR reserved 0x40190018 0x4019001B range 0x4019001C 0x4019001F 4 ReadWrite // MDDSR range 0x40190020 0x40190023 4 ReadWrite // MDIN reserved 0x40190024 0x4019002F range 0x40190030 0x40190033 4 ReadWrite // MDA0 range 0x40190034 0x40190037 4 ReadWrite // MDB0 range 0x40190038 0x4019003B 4 ReadWrite // MDC0 range 0x4019003C 0x4019003F 4 ReadWrite // MDD0 range 0x40190040 0x40190043 4 ReadWrite // MDE0 range 0x40190044 0x40190047 4 ReadWrite // MDMDS reserved 0x40190048 0x4019006F range 0x40190070 0x40190073 4 ReadWrite // MDA1 range 0x40190074 0x40190077 4 ReadWrite // MDB1 range 0x40190078 0x4019007B 4 ReadWrite // MDC1 range 0x4019007C 0x4019007F 4 ReadWrite // MDD1 range 0x40190080 0x40190083 4 ReadWrite // MDE1 reserved 0x40190084 0x4019FFFF // Random Number Generator Registers range 0x401A0000 0x401A0003 4 ReadWrite // RNGCR range 0x401A0004 0x401A0007 4 Read // RNGSR range 0x401A0008 0x401A000B 4 Write // RNGER range 0x401A000C 0x401A000F 4 Read // RNGOUT reserved 0x401A0010 0x401AFFFF // Symmetric Key Hardware Accelerator Registers range 0x401B0000 0x401B0003 4 ReadWrite // SKMR range 0x401B0004 0x401B0007 4 ReadWrite // SKCR range 0x401B0008 0x401B000B 4 ReadWrite // SKCMR range 0x401B000C 0x401B000F 4 Read // SKSR range 0x401B0010 0x401B0013 4 Read // SKESR range 0x401B0014 0x401B0017 4 ReadWrite // SKESMR range 0x401B0018 0x401B001B 4 ReadWrite // SKKSR range 0x401B001C 0x401B001F 4 ReadWrite // SKDSR range 0x401B0020 0x401B0023 4 ReadWrite // SKIN range 0x401B0024 0x401B0027 4 ReadWrite // SKOUT reserved 0x401B0028 0x401B002F range 0x401B0030 0x401B0033 4 Write // SKK1 range 0x401B0034 0x401B0037 4 Write // SKK2 range 0x401B0038 0x401B003B 4 Write // SKK3 range 0x401B003C 0x401B003F 4 Write // SKK4 range 0x401B0040 0x401B0043 4 Write // SKK5 range 0x401B0044 0x401B0047 4 Write // SKK6 reserved 0x401B0048 0x401BFFFF // Flex Controller Area Network 1 Registers range 0x401C0000 0x401C0003 4 ReadWrite // CANMCR1 range 0x401C0004 0x401C0007 4 ReadWrite // CANCTRL1 range 0x401C0008 0x401C000B 4 ReadWrite // TIMER1 reserved 0x401C000C 0x401C000F range 0x401C0010 0x401C0013 4 ReadWrite // RXGMASK1 range 0x401C0014 0x401C0017 4 ReadWrite // RX14MASK1 range 0x401C0018 0x401C001B 4 ReadWrite // RX15MASK1 range 0x401C001C 0x401C001F 4 ReadWrite // ERRCNT1 range 0x401C0020 0x401C0023 4 ReadWrite // ERRSTAT1 reserved 0x401C0024 0x401C0029 range 0x401C002A 0x401C002B 2 ReadWrite // IMASK1 reserved 0x401C002C 0x401C0031 range 0x401C0032 0x401C0033 2 ReadWrite // IFLAG1 reserved 0x401C0034 0x401CFFFF // Enhanced Time Process Unit Registers range 0x401D0000 0x401D0003 4 ReadWrite // ETPU_MCR range 0x401D0004 0x401D0007 4 ReadWrite // ETPU_CDCR reserved 0x401D0008 0x401D000B range 0x401D000C 0x401D000F 4 ReadWrite // ETPU_MISCCMPR reserved 0x401D0010 0x401D0013 range 0x401D0014 0x401D0017 4 ReadWrite // ETPU_ECR reserved 0x401D0018 0x401D001F range 0x401D0020 0x401D0023 4 ReadWrite // ETPU_TBCR range 0x401D0024 0x401D0027 4 ReadWrite // ETPU_TB1R range 0x401D0028 0x401D002B 4 ReadWrite // ETPU_TB2R reserved 0x401D002C 0x401D01FF range 0x401D0200 0x401D0203 4 ReadWrite // ETPU_CISR reserved 0x401D0204 0x401D020F range 0x401D0210 0x401D0213 4 ReadWrite // ETPU_CDTRSR reserved 0x401D0214 0x401D021F range 0x401D0220 0x401D0223 4 ReadWrite // ETPU_CIOSR reserved 0x401D0224 0x401D022F range 0x401D0230 0x401D0233 4 ReadWrite // ETPU_CDTROSR reserved 0x401D0234 0x401D023F range 0x401D0240 0x401D0243 4 ReadWrite // ETPU_CIER reserved 0x401D0244 0x401D024F range 0x401D0250 0x401D0253 4 ReadWrite // ETPU_CDTRER reserved 0x401D0254 0x401D027F range 0x401D0280 0x401D0283 4 Read // ETPU_CPSSR reserved 0x401D0284 0x401D028F range 0x401D0290 0x401D0293 4 Read // ETPU_CSSR reserved 0x401D0294 0x401D03FF range 0x401D0400 0x401D0403 4 ReadWrite // ETPU_C0CR range 0x401D0404 0x401D0407 4 ReadWrite // ETPU_C0SCR range 0x401D0408 0x401D040B 4 ReadWrite // ETPU_C0HSRR reserved 0x401D040C 0x401D040F range 0x401D0410 0x401D0413 4 ReadWrite // ETPU_C1CR range 0x401D0414 0x401D0417 4 ReadWrite // ETPU_C1SCR range 0x401D0418 0x401D041B 4 ReadWrite // ETPU_C1HSRR reserved 0x401D041C 0x401D041F range 0x401D0420 0x401D0423 4 ReadWrite // ETPU_C2CR range 0x401D0424 0x401D0427 4 ReadWrite // ETPU_C2SCR range 0x401D0428 0x401D042B 4 ReadWrite // ETPU_C2HSRR reserved 0x401D042C 0x401D042F range 0x401D0430 0x401D0433 4 ReadWrite // ETPU_C3CR range 0x401D0434 0x401D0437 4 ReadWrite // ETPU_C3SCR range 0x401D0438 0x401D043B 4 ReadWrite // ETPU_C3HSRR reserved 0x401D043C 0x401D043F range 0x401D0440 0x401D0443 4 ReadWrite // ETPU_C4CR range 0x401D0444 0x401D0447 4 ReadWrite // ETPU_C4SCR range 0x401D0448 0x401D044B 4 ReadWrite // ETPU_C4HSRR reserved 0x401D044C 0x401D044F range 0x401D0450 0x401D0453 4 ReadWrite // ETPU_C5CR range 0x401D0454 0x401D0457 4 ReadWrite // ETPU_C5SCR range 0x401D0458 0x401D045B 4 ReadWrite // ETPU_C5HSRR reserved 0x401D045C 0x401D045F range 0x401D0460 0x401D0463 4 ReadWrite // ETPU_C6CR range 0x401D0464 0x401D0467 4 ReadWrite // ETPU_C6SCR range 0x401D0468 0x401D046B 4 ReadWrite // ETPU_C6HSRR reserved 0x401D046C 0x401D046F range 0x401D0470 0x401D0473 4 ReadWrite // ETPU_C7CR range 0x401D0474 0x401D0477 4 ReadWrite // ETPU_C7SCR range 0x401D0478 0x401D047B 4 ReadWrite // ETPU_C7HSRR reserved 0x401D047C 0x401D047F range 0x401D0480 0x401D0483 4 ReadWrite // ETPU_C8CR range 0x401D0484 0x401D0487 4 ReadWrite // ETPU_C8SCR range 0x401D0488 0x401D048B 4 ReadWrite // ETPU_C8HSRR reserved 0x401D048C 0x401D048F range 0x401D0490 0x401D0493 4 ReadWrite // ETPU_C9CR range 0x401D0494 0x401D0497 4 ReadWrite // ETPU_C9SCR range 0x401D0498 0x401D049B 4 ReadWrite // ETPU_C9HSRR reserved 0x401D049C 0x401D049F range 0x401D04A0 0x401D04A3 4 ReadWrite // ETPU_C10CR range 0x401D04A4 0x401D04A7 4 ReadWrite // ETPU_C10SCR range 0x401D04A8 0x401D04AB 4 ReadWrite // ETPU_C10HSRR reserved 0x401D04AC 0x401D04AF range 0x401D04B0 0x401D04B3 4 ReadWrite // ETPU_C11CR range 0x401D04B4 0x401D04B7 4 ReadWrite // ETPU_C11SCR range 0x401D04B8 0x401D04BB 4 ReadWrite // ETPU_C11HSRR reserved 0x401D04BC 0x401D04BF range 0x401D04C0 0x401D04C3 4 ReadWrite // ETPU_C12CR range 0x401D04C4 0x401D04C7 4 ReadWrite // ETPU_C12SCR range 0x401D04C8 0x401D04CB 4 ReadWrite // ETPU_C12HSRR reserved 0x401D04CC 0x401D04CF range 0x401D04D0 0x401D04D3 4 ReadWrite // ETPU_C13CR range 0x401D04D4 0x401D04D7 4 ReadWrite // ETPU_C13SCR range 0x401D04D8 0x401D04DB 4 ReadWrite // ETPU_C13HSRR reserved 0x401D04DC 0x401D04DF range 0x401D04E0 0x401D04E3 4 ReadWrite // ETPU_C14CR range 0x401D04E4 0x401D04E7 4 ReadWrite // ETPU_C14SCR range 0x401D04E8 0x401D04EB 4 ReadWrite // ETPU_C14HSRR reserved 0x401D04EC 0x401D04EF range 0x401D04F0 0x401D04F3 4 ReadWrite // ETPU_C15CR range 0x401D04F4 0x401D04F7 4 ReadWrite // ETPU_C15SCR range 0x401D04F8 0x401D04FB 4 ReadWrite // ETPU_C15HSRR reserved 0x401D04FC 0x401D04FF range 0x401D0500 0x401D0503 4 ReadWrite // ETPU_C16CR range 0x401D0504 0x401D0507 4 ReadWrite // ETPU_C16SCR range 0x401D0508 0x401D050B 4 ReadWrite // ETPU_C16HSRR reserved 0x401D050C 0x401D050F range 0x401D0510 0x401D0513 4 ReadWrite // ETPU_C17CR range 0x401D0514 0x401D0517 4 ReadWrite // ETPU_C17SCR range 0x401D0518 0x401D051B 4 ReadWrite // ETPU_C17HSRR reserved 0x401D051C 0x401D051F range 0x401D0520 0x401D0523 4 ReadWrite // ETPU_C18CR range 0x401D0524 0x401D0527 4 ReadWrite // ETPU_C18SCR range 0x401D0528 0x401D052B 4 ReadWrite // ETPU_C18HSRR reserved 0x401D052C 0x401D052F range 0x401D0530 0x401D0533 4 ReadWrite // ETPU_C19CR range 0x401D0534 0x401D0537 4 ReadWrite // ETPU_C19SCR range 0x401D0538 0x401D053B 4 ReadWrite // ETPU_C19HSRR reserved 0x401D053C 0x401D053F range 0x401D0540 0x401D0543 4 ReadWrite // ETPU_C20CR range 0x401D0544 0x401D0547 4 ReadWrite // ETPU_C20SCR range 0x401D0548 0x401D054B 4 ReadWrite // ETPU_C20HSRR reserved 0x401D054C 0x401D054F range 0x401D0550 0x401D0553 4 ReadWrite // ETPU_C21CR range 0x401D0554 0x401D0557 4 ReadWrite // ETPU_C21SCR range 0x401D0558 0x401D055B 4 ReadWrite // ETPU_C21HSRR reserved 0x401D055C 0x401D055F range 0x401D0560 0x401D0563 4 ReadWrite // ETPU_C22CR range 0x401D0564 0x401D0567 4 ReadWrite // ETPU_C22SCR range 0x401D0568 0x401D056B 4 ReadWrite // ETPU_C22HSRR reserved 0x401D056C 0x401D056F range 0x401D0570 0x401D0573 4 ReadWrite // ETPU_C23CR range 0x401D0574 0x401D0577 4 ReadWrite // ETPU_C23SCR range 0x401D0578 0x401D057B 4 ReadWrite // ETPU_C23HSRR reserved 0x401D057C 0x401D057F range 0x401D0580 0x401D0583 4 ReadWrite // ETPU_C24CR range 0x401D0584 0x401D0587 4 ReadWrite // ETPU_C24SCR range 0x401D0588 0x401D058B 4 ReadWrite // ETPU_C24HSRR reserved 0x401D058C 0x401D058F range 0x401D0590 0x401D0593 4 ReadWrite // ETPU_C25CR range 0x401D0594 0x401D0597 4 ReadWrite // ETPU_C25SCR range 0x401D0598 0x401D059B 4 ReadWrite // ETPU_C25HSRR reserved 0x401D059C 0x401D059F range 0x401D05A0 0x401D05A3 4 ReadWrite // ETPU_C26CR range 0x401D05A4 0x401D05A7 4 ReadWrite // ETPU_C26SCR range 0x401D05A8 0x401D05AB 4 ReadWrite // ETPU_C26HSRR reserved 0x401D05AC 0x401D05AF range 0x401D05B0 0x401D05B3 4 ReadWrite // ETPU_C27CR range 0x401D05B4 0x401D05B7 4 ReadWrite // ETPU_C27SCR range 0x401D05B8 0x401D05BB 4 ReadWrite // ETPU_C27HSRR reserved 0x401D05BC 0x401D05BF range 0x401D05C0 0x401D05C3 4 ReadWrite // ETPU_C28CR range 0x401D05C4 0x401D05C7 4 ReadWrite // ETPU_C28SCR range 0x401D05C8 0x401D05CB 4 ReadWrite // ETPU_C28HSRR reserved 0x401D05CC 0x401D05CF range 0x401D05D0 0x401D05D3 4 ReadWrite // ETPU_C29CR range 0x401D05D4 0x401D05D7 4 ReadWrite // ETPU_C29SCR range 0x401D05D8 0x401D05DB 4 ReadWrite // ETPU_C29HSRR reserved 0x401D05DC 0x401D05DF range 0x401D05E0 0x401D05E3 4 ReadWrite // ETPU_C30CR range 0x401D05E4 0x401D05E7 4 ReadWrite // ETPU_C30SCR range 0x401D05E8 0x401D05EB 4 ReadWrite // ETPU_C30HSRR reserved 0x401D05EC 0x401D05EF range 0x401D05F0 0x401D05F3 4 ReadWrite // ETPU_C31CR range 0x401D05F4 0x401D05F7 4 ReadWrite // ETPU_C31SCR range 0x401D05F8 0x401D05FB 4 ReadWrite // ETPU_C31HSRR reserved 0x401D05FC 0x401EFFFF // Flex Controller Area Network 2 Registers range 0x401F0000 0x401F0003 4 ReadWrite // CANMCR2 range 0x401F0004 0x401F0007 4 ReadWrite // CANCTRL2 range 0x401F0008 0x401F000B 4 ReadWrite // TIMER2 reserved 0x401F000C 0x401F000F range 0x401F0010 0x401F0013 4 ReadWrite // RXGMASK2 range 0x401F0014 0x401F0017 4 ReadWrite // RX14MASK2 range 0x401F0018 0x401F001B 4 ReadWrite // RX15MASK2 range 0x401F001C 0x401F001F 4 ReadWrite // ERRCNT2 range 0x401F0020 0x401F0023 4 ReadWrite // ERRSTAT2 reserved 0x401F0024 0x401F0029 range 0x401F002A 0x401F002B 2 ReadWrite // IMASK2 reserved 0x401F002C 0x401F0031 range 0x401F0032 0x401F0033 2 ReadWrite // IFLAG2 reserved 0x401F0034 0x401FFFFF