ICSP Programming Header +3.3V GND MCLR DATA CLOCK I/O header PWR MODE VREG BPv3.9 PWR MODE VREG USB USB 5V GND ADC CS CLK 3V3 VPU AUX MISO MOSI Seeed Studio www.seeedstudio.com I+S 2018 Ian Lesnet Fulfillment by Bus Pirate FEB 2018 v3.9 CC-0 Ian Lesnet Bus Pirate v3.9 FEB 2018 http://dangerousprototypes.com PGC PGD GND +3V3 !MLCR GND 3V3 ADC CS CLK MOSI MISO AUX VPU 5V v.trocio NC NC ICSP <b>Chip Capacitor </b> Polar tantalum capacitors with solid electrolyte<p> Siemens Matsushita Components B 45 194, B 45 197, B 45 198<br> Source: www.farnell.com/datasheets/247.pdf >NAME >VALUE SMD Wire Wound Ceramic Inductor >VALUE >NAME <b>plastic thin shrink small outline package; 14 leads; body width 4.4 mm</b><p> SOT402-1<br> Source: http://www.nxp.com/documents/data_sheet/74ABT125.pdf >NAME >VALUE >NAME >VALUE >NAME >VALUE >NAME >VALUE SSOP28 >NAME >VALUE >NAME >VALUE /home/buglabs/Downloads/oshw_temp.bmp Dangerous Prototypes Standard PCB sizes http://dangerousprototypes.com SSOP-16, 0.32 x 1.26 mm pad, 0.63mm pitch, 6.82mm Pad length >NAME >VALUE 50mm 50mm D = 3.2mm 4.0mm R = 4.0mm Center Center >PCB_SIZE 1-MD05SNXXX-01 <br>Micro USB 5P/F B Type SMT >NAME Molex PN: 70553-0044 <br> Distance from edge to center: 6.795 mm >NAME >VALUE >NAME >VALUE <b>Dirty Cheap Dirty Board Design Rules</b> <br> <br>Min width/Spacing: 6/6mil <br>Min diameter of finished hole 12mil <b>Dirty Cheap Dirty Board Design Rules</b> <br> <br>Min width/Spacing: 6/6mil <br>Min diameter of finished hole 12mil <b>Dirty Cheap Dirty Board Design Rules</b> <br> <br>Min width/Spacing: 6/6mil <br>Min diameter of finished hole 12mil